IC Design Center
In order to achieve self reliance in electronics and develop indigenous electronics products, acquisition of IC technology is necessary. It is imperative that a comprehensive capacity building program is initiated. The IC Design Center of National Institute of Electronics (NIE) provides complete environment for design capture, physical layout and verification of digital, analog and mixed-signal integrated circuits. The Center is powered by EDA tools from Mentor Graphics USA on Linux and Windows based platforms. The software provides advanced set of features for floor planning, top level assembly, interactive routing, physical verification DRC/LVS, parasitic extraction, and efficient polygon editing. The design is converted to physical mask database in GDS-II format enabling to export out design to any leading foundry.
The main aim of the center is the capacity building and training of Engineers / Scientists in the field of IC design and technology. The Center will also provide IC design services to industry and other R & D organizations involved in design and development of electronic systems & circuits. Initially the center will provide training to engineers, scientists and researchers from universities and R & D organizations. The facility will be opened for university students and researchers for their projects. In order to give full concept of IC Design technology, the student project chips will be fabricated from abroad using Multi Project Wafer (MPW) fabrication technology. MPW fabrication technology is cost effective and suitable for student project designs.
An advanced IC Design facility equipped with state-of-the-art IC Design Tools has been established. The Design Center provides complete environment for design capture, physical layout and verification of digital, analog and mixed signal integrated circuits. IC Design Tools from Mentor Graphics USA have been selected for IC nanometer design. Linux and Windows based platforms / workstations have been selected. Mentor Graphics tools are supported by the major foundries of the world. The software provides advanced set of features for physical layout, floor planning, top level assembly, interactive routing, physical verification DRC/LVS, parasitic extraction, and efficient polygon editing. The design is converted to physical mask database in GDS-II format enabling to export out design to any leading foundry.
IC Design Center
The IC Design Center offers following services to the Industry and R & D organizations:
- Technical feasibility analysis and design methodology selection
- System partitioning
- Logic conversion from discrete logic to specific cell macros
- Schematic Capture & netlist Generation
- Logic and timing simulation
- Physical layout, auto placement and routing
- Fault simulation and testability analysis
- Electrical and physical design rule check (ERC & DRC)
- Layout Versus Schematic verification (LVS)
- Parasitic extraction
- Test Vector generation
- Mask preparation (GDS II Format)
- Interface with foundries and MPW service providers.
Outsourcing IC Design Services
The Design center will also provide IC Design services to international companies.
IC Design Center
The Center has developed special courses for students, researchers and Universities faculty. The detail of the course is as under :
Course Title: IC Nanometer Design.
The course will provide knowledge required to design, physical layout & verification of digital and analog chips using Mentor Graphics IC design Tools. There would be extensive lectures on explaining concepts and evolution of EDA design flow and fabrication techniques.
Throughout the course, the lectures will be followed by hand-on lab sessions to help participants acquire the skills to capture and simulate the design, create layout using advanced routing and floor planning tools, and finally perform design verifications.
Module I (Design Capture)
This module covers all the important aspects of schematic capture. The participants are guided through major steps of schematic creation and editing. Apart from all this, extensive lab sessions are arranged to help them get familiar with important options of Pyxis Schematic that are readily used during designing. The module primarily covers the following two areas:
- Creat and edit schematics in Pyxis Schematic.
- Import HDL description for design elements using Leonardo Spectrum.
Module II (Digital & Analog Simulation)
Simulation of a design is very important phase of IC Design flow. A successful simulation is the first step to guarantee the perfect results of a design. This module has been planned to cover the simulation procedures of two major types of design flows i.e. digital and analog. The module helps the participants to learn simulate their designs using following toolset:
- Setup and run simulation using Eldo Simulator and analyse results in EZwave.
Module III (Physical Layout)
The most important phase of IC Design flow is generating the layout. This module has been designed keeping in view the fact that mask designing is not taught in various curriculums of Electrical and Electronics Engineering. The participants will be given a good overview of issues regarding layout designing. The lab sessions will start with the Layout generation of basic electronic designs followed by some very complex digital chips. The module will majorly cover areas like:
- Full custom layout creation & polygon editing.
- Creating and editing IC Layouts through interactive place and route using LDL-cokpit.
- Use schematic-driven layout (SDL) to automated generation of layout.
- Perform routing using automated (ARoute) and interactive routing (IRoute) techniques.
- Auto floor planning and placement using ICassemble.
Module IV (Physical Verification)
The design flow completes with the verification of designs using standard design rules provided by the industry. This module covers all the important rule checking techniques using the design rules of advance foundries of the world. The participants are guided through all the rules checking techniques so that they could easily verify their designs in future. The module mainly covers the following areas of design verification:
- Translation of layout to GDSII format.
- Perform post layout verification using Calibre DRC/LVS.
Timing : 9:00 AM to 1:00 PM
Fee : Rs. 10,000/- (For Professionals)
Rs. 5000/- (For Students)
IC Design Center
Integrated Circuit Design Center,
National Institute of Electronics, Plot # 17, Street # 6, H-9/1, Islamabad
Exchange No: (+92)-51-9265029
Email: firstname.lastname@example.org , email@example.com